1. Field of the Invention
The present invention relates to digital logic gates. More particularly, the present invention relates to digital logic gate designs using negative differential resistance diodes and metal oxide semiconductor field effect transistors (MOSFETs) or heterostructure field effect transistors.
2. Background Information
Digital logic gates typically incorporate p-type metal oxide semiconductor (MOS) transistors which are used for precharging and storage in dynamic complementary metal oxide semiconductor (CMOS) logic. Dynamic CMOS circuits are susceptible to noise due to capacitive coupling or leakage current from MOSFETs. These phenomena adversely affect circuit operation since the circuit output is not held by a conducting MOSFET on removal of the input signal. Another problem with dynamic CMOS gates is charge sharing which reduces the output high voltage possibly causing logic errors.
Prior quantum circuit approaches have used (negative differential resistance (NDR) diodes) along with resistive loads for logic function implementation. This results in high power dissipation and also the use of precision resistors increases the size of the circuit since resistors are not easily fabricated in an integrated form using small areas.
Other circuits have been proposed which use bipolar transistors in conjunction with NDR diodes such as resonant tunneling diodes. While these circuits possess high operating speed, they have the disadvantage of high power dissipation and low noise margins due to low voltage swings. These circuits are difficult to design since the loading effect of the subsequent inputs on the output of a logic gate can change the circuit function.
Bistable mode circuits, in earlier quantum circuit technologies, typically require a multi-phase (AC) power supply that is used to periodically reset/evaluate a gate. This has the disadvantage of requiring an AC power supply which determines the maximum frequency of operation. Conventional circuit techniques, such as CMOS, use discrete latching elements to achieve bistable mode operation. The addition of the latching elements results in increased circuit size and delay.
Thus, there is a need for a high performance digital logic gate which is reliable and less susceptible to noise. There is also a need for a digital logic gate which has a high speed of operation, small size, and low power dissipation. There is a further need for a digital logic gate which operates in the bistable operation mode without requiring an AC power supply or discrete latching elements.